The present invention relates generally to a method of fabricating a 3-dimensional fan-out structure and, more particularly to a method of fabricating a 3-dimensional fan-out structure for an integrated circuit device.
Fan-out wafer level packaging (WLP) enables 3-dimensional (3D) structures to be implemented within integrated circuit devices through vertical integration of semiconductor dies within a single integrated circuit package. As such, fan-out WLP has become an important technique for increasing the functionality that can be integrated within a single integrated circuit device.
Conventional techniques for fabricating wafer level fan-out within an integrated circuit device typically involve processes such as panelization processes, through package via processes and double sided build-up processes. Such processes add significant cost, manufacturability and reliability issues to the fabrication of wafer level fan-out within integrated circuit devices.
For example, with conventional FOWLP (Fan-Out Wafer Level Package) fabrication, the die and components are usually placed onto a temporary tape/carrier ‘face down’ (i.e., ‘active’ side in contact with the tape/carrier) to make sure the die and components are co-planar. Encapsulation follows to assemble the die and components into a ‘panel’ form ready for build-up. In order to perform the build-up on the active side of the die and components, the panel is flipped over and the tape/carrier removed. The tape/carrier removal process usually involves specialized thermal, optical or mechanical processes which complicate the production flow and increase cost. At the same time, because the die and components are placed prior to encapsulation, shrinking of the encapsulant can cause ‘die drift’, which can result in a large yield loss. Die drift is especially problematic when FOWLP is used for large panel sizes and with fine pitch products.
In addition to the complication of process flow and challenge of die drift, the taping/carrier process can also result in undesired topography on the panel. This is due to the die/components penetrating into the tape/carrier adhesive during placement, as illustrated in FIG. 1. As a result, when subsequently encapsulated and the tape/carrier removed, the regions of the die/components that penetrated the adhesive will protrude from the surface of the encapsulant creating chip-to-mold or component-to-mold non-planarity, as illustrated in FIG. 2. Such non-planarity can impact build-up layer continuity and create stress at the die/component level following build-up of the redistribution layers, potentially resulting in damage to the dies/components and the redistribution layers, as well as resulting in adhesive voids.
Accordingly, a technique for fabricating wafer level fan-out within an integrated circuit device that does not involve such lengthy, high yield loss and complicated processes would help to reduce the cost and improve the manufacturability and reliability of such integrated circuit devices.